The present invention generally relates to semiconductor fabrication and, more particularly, to a method for controlling the flow of wafer lots within the semiconductor fabrication facility and a fabrication facility employing such method.
Semiconductor manufactures compete in a highly competitive and capital-intensive industry. A state-of-the-art semiconductor fabrication plant typically includes hundreds of different fabrication tools and can cost $1 billion or more. New plants can also become obsolete relatively quickly as the dimensions of semiconductor devices decrease.
FIG. 1 schematically illustrates, albeit in a relatively simple form, a conventional semiconductor fabrication plant 100. The fabrication plant 100 includes multiple fabrication areas or bays 110 interconnected by a path 120, such as a conveyor belt. Each bay 110 generally includes the requisite processing tools (interconnected by a subpath) to process semiconductor wafers for a particular purpose, such as photolithography, chemical-mechanical polishing, or chemical vapor deposition, for example. Material stockers 130 generally lie about the plant 100 and store semiconductor wafers waiting to be processed. The wafers are typically stored in cassettes each of which can hold up to 25 wafers. Each material stocker 130 typically services two or more bays 110 and can hold hundreds of cassettes. While not shown, the semiconductor fabrication plant 100, including the bays 110, material stockers 130 and the interconnecting path 120, typically operates under control of a host system, usually a distributed computer system running a factory management program, such as WorkStream Open sold by Consilium, Inc.
A typical semiconductor fabrication plant, such as the one described above, handles the processing of thousands of wafers at any given time. The wafers are typically divided into batches which undergo different processing flows. During processing, bubbles or log jams of wafer lots typically occur. Such bubbles may occur for a variety of reasons. For instance, the process flows of different wafer batches may meet at a particular area, such as a bay, stocker or processing tool, and cause a bubble at the particular area. Bubbles not only affect processing at the bubble point, but also cause a ripple effect which slows upstream processing as well. This significantly degrades wafer throughput in the fabrication facility.
The present invention generally provides techniques for controlling the flow of wafer lots in a semiconductor fabrication facility having multiple storage locations and a fabrication facility employing such techniques. The invention may, for example, advantageously anticipate or sense bubbles or log jams of wafer lots in a fabrication facility and redirect wafer lots in order to avoid or reduce any bubble effect. This can, for example, significantly increase the throughput of wafers through the fabrication facility.
A process and system for controlling the flow of wafer lots within a semiconductor fabrication facility, in accordance with one embodiment of the invention, includes determining a first storage location for a wafer lot, determining, prior to moving the wafer lot, an availability condition of the first storage location based on a condition level of the first storage location and a priority of the wafer lot, and storing the wafer lot in the storage location if the location is available and storing the wafer lot in an alternate location if the storage location is unavailable. The storage location may, for example, be a stocker or a buffer or bin associated with a bay or a processing tool.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures in the detailed description which follow more particularly exemplify these embodiments.
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
FIG. 1 schematically illustrates a conventional semiconductor fabrication facility;
FIG. 2 schematically illustrates an exemplary semiconductor fabrication facility in accordance with one embodiment of the invention;
FIG. 3 illustrates an exemplary process in accordance with another embodiment of the invention;
FIG. 4 is a table illustrating exemplary condition levels in accordance with one embodiment of the invention;
FIG. 5 is a table illustrating exemplary priority levels in accordance with another embodiment of the invention;
FIG. 6 is a table illustrating exemplary acceptance rules in accordance with another embodiment of the invention; and
FIG. 7 illustrates another exemplary process in accordance with an embodiment of the invention.